In forming damascene structures in integrated, circuit manufacturing processes, the surface condition of the damascene opening is critical for achieving acceptable adhesion and coverage of overlying layers. The damascene opening, for example a dual damascene opening is formed in an inter-metal dielectric insulating layer in a series of photolithographic patterning and etching processes, followed by formation of a barrier layer and a metal filling process.
Increasingly, low-K layers are required to reduce signal delay and power loss effects as integrated circuit devices are scaled down. One way this has been accomplished has been to introduce porosity or dopants into the dielectric insulating layer, also referred to as an inter-metal dielectric (IMD) layer.
As a result, the need for lower dielectric constant materials has resulted in the development of several different types of organic and inorganic low-k materials. In particular, incorporation of low-k materials with dielectric constants less than about 3.0 has become standard practice as semiconductor feature sizes have diminished to less than 0.2 microns. As feature sizes decrease below 0.2 microns, for example to 0.13 microns and below, materials with dielectric constants less than about 2.5 will be required. Several different organic and inorganic low-k materials have been developed and proposed for use in semiconductor devices as insulating material having dielectric constants less than about 3.0.
For example, porous silicon oxide based materials are formed by including a carbon based moiety which forms an Si—O—C type structure which then forms a porous structure following deposition and curing or treatment processes, In prior art processes the entire IMD layer has been deposited in a single step process where the entire IMD layer has about the same density or porosity volume throughout the IMD layer.
One problem with using porous low-k materials has been the difficulty of adapting conventional plasma assisted etching processes to reliably and consistently etch openings in an IMD layer. For example, the selectivity including the anisotropicity of the etching process becomes more complex as more porosity is introduced into the IMD layer to achieve lower dielectric constants. As a result, etching profiles of high aspect ratio openings, for example greater than about 4 to 1, have become more difficult to control. In addition, as the IMD layer becomes less dense, the distribution of pores may increasingly vary to the extent that etching rates vary upon etching through a thickness of the IMD layer.
Another problem related to etched openings in low-K IMD layers having an increased porosity to achieve lower dielectric constants, is the presence of a relatively rough surface due to the penetration of pore openings at the surface of the etched opening. The micro-roughness at the surface adversely affects the adhesion and coverage of overlying deposited layers, for example barrier layers. As a result, thicker barrier layers, with increased series resistance are required in order to avoid forming barrier layers having pinholes which undesirably allow electromigration of metal into the IMD layer. Further the deposition of seed layers may be non-continuously formed, thereby adversely affecting electro-chemical deposition processes. The various problems are exacerbated in higher aspect ratio holes such as via portions of a dual damascene. The various problems with low-K IMD layers including an etching profile and etched opening surface condition therefore undesirably affect yield and reliable electrical operation of an IC device.
There is therefore a need in the integrated circuit manufacturing art to develop a manufacturing process whereby porous low-K dielectric layers may be formed to improve the reliability of formation of etched openings including an etching profile and surface roughness to improve integrated circuit device yield and reliability.
It is therefore among the objects of the present invention to provide a manufacturing process whereby porous low-K dielectric layers may be formed to improve the reliability of formation of etched openings including an etching profile and surface roughness to improve integrated circuit device yield and reliability, while overcoming other shortcomings of the prior art.